Periodic digital signals are commonly used in a variety of electronic devices. Probably the most common type of periodic digital signals are clock signals that are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a data strobe signal. The data strobe signal typically has a phase that is aligned with a system clock signal. Write data signals are typically coupled from the memory controller in synchronism with a write data strobe signal. The write data signals are typically the quadrature of the write strobe signal so that the write data strobe signal transitions between two logic levels during a “data eye” occurring at the center of the period in which the data signals are valid. The write data strobe signal can therefore be used by the memory device to latch or “capture” the write data. Read data signals are typically coupled from a memory device in synchronism with a read data strobe signal. The read data signals typically have the same phase as the read data strobe signal. However, the read data strobe signal is normally used by the memory controller to generate a quadrature signal that can be used by the memory controller to “capture” the read data.
As the speed of memory devices has continued to increase, the “data eye” has become smaller and smaller, thus making the timing of the data strobe signals relative to the timing of the data signals even more critical. One difficulty that has been encountered in ensuring that data strobe signals transition at the proper time is the variability in quality of the data strobe signal. In particular, when a data strobe signal line has been idle, the first data strobe signal typically does not have well defined transitions, as shown at times t0 and t1 in FIG. 1. The difficulty in transitioning the data strobe signal line when the line has been idle results from the line becoming heavily charged to a bias voltage, typically one-half the supply voltage VCC in a center tapped termination (“CTT”) system or the supply voltage VCC in an alternative (“VDD”) system. However, after the initial data strobe pulse, the transitions of the data strobe signal become well defined at time t2, t3 and subsequent times. At the relatively slow operating speeds of conventional memory devices, the relatively undefined transitions of the initial data strobe pulse are still able to capture the data signals. However, as the operating speeds of memory devices continues to increase, it is becoming increasingly difficult for the data strobe signal to capture the first bit or two of data.
One approach that has been used to avoid the problems created by the relatively undefined transitions of the initial data strobe signals is to provide a “preamble” prior to the receipt of valid data signals during which unused data strobe signals are transmitted. As shown in FIG. 2, a preamble of two data strobe signals transitioning at times t0, t1, t2 and t3 precede a strobe signal transitioning at time t4 which is used to capture valid data. As shown in FIG. 2, the transitions occurring at time t0 and t1 are not well defined, and the transitions occurring at times t2 and t3 are less well defined by subsequent transitions. However, the transitions occurring at time t5 and subsequent times are well defined, and can therefore be used to more accurately capture the data signals.
Unfortunately, it can be difficult to determine when valid data signals are being received, and it can be difficult to differentiate actual data strobe signals from data strobe signals occurring in the preamble. This difficulty is exacerbated by the fact that strobe signals preambles are not needed when data transfers occur on a sequential basis, e.g., two write accesses in a row, thus making the data strobe signal continuously present. In fact, providing a preamble under these circumstances would reduce the data bandwidth of the memory device because no data would be transferred during the unnecessary preamble. For example, as shown in FIG. 2, if data signals were being captured prior to time t0, the presence of the preamble between times t0 and t4 would waste over two clock periods of time.
Another problem with proposed data strobe preamble schemes results from the fact that the data strobe signals are in a clock domain that is different from the clock domain of the system clock signal and command signals. The timing relationship between the data strobe signal and the start of valid data signals is therefore not easily determined and can vary considerably. For example, although the system clock signal is in general alignment with the data strobe signal, the specification for typical SDRAM memory devices allows this timing relationship to vary by plus or minus one-quarter period of the CLK signal. Insofar as the command signals are in the same clock domain as the system clock signal, the timing relationship between the data strobe signals and the command signals can vary in this same manner. Also, depending on signal termination techniques and system frequency, false or missing toggles could be present on the data strobe compromising reliability of initial strobe toggles. As a result, it is not possible, for example, to simply delay for two transitions of the data strobe signal after receipt of a command signal before using the data strobe signal to capture data signals. At the relatively slow operating speeds of conventional memory devices, it has generally been possible to determine when valid data signals are being received and should therefore be captured by received data strobe signals. However, with ever increasing operating speeds of memory devices, it is becoming increasingly difficult to make this determination.
There is therefore a need for a method and system of allowing read and write data signals to be accurately captured when a memory device is operating at a very high rate of speed.